ISTQB CTAL-TM_001 Q&A - in .pdf

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  • Exam Code: CTAL-TM_001
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  • Exam Code: CTAL-TM_001
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NEW QUESTION: 1
When an ARMv7-A MPCore system is in SMP mode, which of the following TWO operations can the processor handle automatically? (Choose two)
A. Coherency management between all L1 data caches
B. Coherency management between all L1 instruction caches
C. Broadcast of some outer-shared cache and TLB maintenance operations
D. Broadcast of some inner-shared cache and TLB maintenance operations
E. Coherency management between all external caches
Answer: A,D

NEW QUESTION: 2
Refer to the exhibit.

Given the following GUI output on an autonomous AP, how many additional infrastructure APs are registered to the Cisco WDS AP that is shown in the exhibit, and which Cisco WDS master AP MAC address is used for the WDS registration process?
A. One and 0026.cb53.6d40
B. One and 0024.d70c.7ca4 or 001b.7766.d253
C. Zero and 0026.cb53.6d40
D. Zero and 0022.bd1a.0680
E. Two and 0026.cb53.6d40
F. One and 0022.bd1a.0680
Answer: F

NEW QUESTION: 3

A. Parent
B. Natural
C. Recursive
D. Explicit
Answer: C
Explanation:
Reference: http://technet.microsoft.com/en-us/library/ff487006.aspx
Reference: http://msdn.microsoft.com/en-us/library/ee633747.aspx
Reference: http://technet.microsoft.com/en-us/library/ee633759.aspx

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