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NEW QUESTION: 1
When microcomputers were first developed, the instruction fetch time
was much longer than the instruction execution time because of the
relatively slow speed of memory accesses. This situation led to the
design of the:
A. Reduced Instruction Set Computer (RISC)
B. Complex Instruction Set Computer (CISC)
C. Superscalar processor
D. Very-Long-Instruction-Word (VLIW) processor
Answer: B
Explanation:
The logic was that since it took a long time to fetch an instruction from memory relative to the time required to execute that instruction in the CPU, then the number of instructions required to implement a program should be reduced. This reasoning naturally resulted in densely coded instructions with more decode and execution cycles in the processor. This situation was ameliorated by pipelining the instructions wherein the decode and execution cycles of one instruction would be overlapped in time with the fetch cycle of the next instruction.
*Answer "Reduced Instruction Set Computer (RISC)", RISC, evolved when packaging and memory technology advanced to the point where there was not much difference in memory access times and processor execution times. Thus, the objective of the RISC architecture was to reduce the number of cycles required to execute an instruction. Accordingly, this increased the number of instructions in the average program by approximately 30%, but it reduced the number of cycles per instruction on the average by a factor of four. Essentially, the RISC architecture uses simpler instructions but makes use of other features such as optimizing compilers to reduce the number of instructions required and large numbers of general purpose registers in the processor and data caches.
*The superscalar processor, answer "Superscalar processor",
allows concurrent execution of instructions in the same pipelined stage. A scalar processor is defined as a processor that executes one instruction at a time. The term superscalar denotes multiple, concurrent operations performed on scalar values as opposed to vectors or arrays that are used as objects of computation in array processors.
*For answer "Very-Long-Instruction-Word (VLIW) processor" multiple, concurrent operations are performed in a single instruction. Because multiple operations are performed in one instruction rather than using multiple instructions, the number of instructions is reduced relative to those in a scalar processor. However, for this approach to be feasible, the operations in each VLIW instruction must be independent of each other.

NEW QUESTION: 2
In which of the following steps of incident response does a team analyze the incident and determine steps to prevent a future occurrence?
A. Identification
B. Lessons learned
C. Preparation
D. Mitigation
Answer: B
Explanation:
Explanation/Reference:
Explanation:
Incident response procedures involve in chronological order: Preparation; Incident identification; Escalation and notification; Mitigation steps; Lessons learned; Reporting; Recover/reconstitution procedures; First responder; Incident isolation (Quarantine; Device removal); Data breach; Damage and loss control. Thus, lessons are only learned after the mitigation occurred. For only then can you 'step back' and analyze the incident to prevent the same occurrence in the future.

NEW QUESTION: 3
Which option is the result if two adjacent routers are configured for OSPF with different process IDs?
A. The routers establish an adjacency and exchange routes, but the routes are unreachable.
B. The routers establish an adjacency and exchange routes, and the routes are reachable.
C. The routers establish an adjacency, but route exchange fails.
D. The routers are unable to establish an adjacency.
Answer: B